100 LEVEL CELANROOM MICROBARICATION
100 LEVEL CELANROOM MICROBARICATION
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At Michigan State University, I completed a series of cleanroom-based fabrication labs for ECE 477 Microtechnology course (Ongoing) that guided me through the full process of semiconductor device manufacturing—from wafer preparation and oxidation to photolithography, diffusion, and gate oxide formation. These hands-on experiences allowed me to apply theoretical concepts of semiconductor physics in a practical setting, develop strong technical precision, and gain a deep appreciation for the workflow and discipline required in modern microfabrication.
Four-Point Probe and Wafer Characterization
Four-Point Probe and Wafer Characterization
Our first lab introduced the fundamentals of silicon wafer characterization. I measured the sheet resistance of p-type wafers using a four-point probe system, ensuring contact-resistance-free readings by applying current through the outer probes and measuring voltage between the inner probes. After cleaning the wafer and tweezers with acetone, methanol, and deionized water, I recorded multiple V/I readings, averaged them, and calculated resistivity and doping concentration using correction factors and resistivity-vs-doping graphs. This process enhanced my understanding of semiconductor material properties, resistivity measurement principles, and cleanroom contamination control.
Skills learned: Semiconductor material characterization, data analysis, contamination-free handling, and use of precision electrical measurement instruments.
Wafer Cleaning and Field Oxide Growth
Wafer Cleaning and Field Oxide Growth
In our second lab, we performed RCA cleaning and thermal oxidation to grow a high-quality SiO₂ layer on p-type silicon. The process began with degrease and demetal etches using NH₄OH/H₂O₂/H₂O and HCl/H₂O₂/H₂O solutions, followed by rinsing and nitrogen drying. The oxidation was conducted at 1000 °C with a controlled sequence of dry-wet-dry oxidation steps under oxygen flow, and finally annealed in nitrogen to stabilize the oxide. This field oxide served as a diffusion mask for later fabrication steps
Skills learned: RCA cleaning, furnace operation, thermal oxidation kinetics, safety in chemical handling, and understanding oxide-growth mechanisms.
Photolithography with Mask 1
Photolithography with Mask 1
In this step, I patterned the oxide layer using standard photolithography. I first measured the oxide thickness using an ellipsometer, then spin-coated a positive photoresist at 3000 rpm and soft-baked it at 115 °C. Using a mask aligner, I aligned and exposed the wafer under UV light through Mask 1, developed the photoresist, and etched oxide windows with buffered HF. After the pattern transfer, I stripped the remaining resist. This process provided practical experience in optical alignment, resist processing, and micro-scale pattern definition.
Skills learned: Photolithography alignment, resist spin-coating, optical exposure, oxide etching, and cleanroom workflow discipline.
Phosphorus Pre-Deposition Diffusion
Phosphorus Pre-Deposition Diffusion
I carried out phosphorus diffusion to introduce n-type dopants into silicon through the lithographically defined oxide openings. Following an RCA clean, I loaded the wafer into a quartz boat and inserted it into a 900 °C furnace under N₂ flow. The pre-deposition lasted one hour, forming a phosphosilicate glass layer on the surface, which was later removed using a diluted HF solution. This step taught me about dopant incorporation, diffusion physics, and how pre-deposition establishes shallow junctions.
Skills learned: Thermal diffusion process control, furnace loading/unloading techniques, dopant safety handling, and chemical etching.
Drive-In Diffusion and Annealing
Drive-In Diffusion and Annealing
In this continuation of the diffusion process, I performed a drive-in anneal at 1000 °C to push the pre-deposited phosphorus deeper into the silicon substrate. After cleaning, I loaded the wafer into the furnace, carried out sequential dry and wet oxidations, and switched to nitrogen for the annealing step. The oxidation not only grew an oxide cap but also helped activate dopants and repair lattice damage. I completed the process by cooling the wafer under controlled flow conditions.
Skills learned: Diffusion modeling, oxidation-assisted drive-in techniques, annealing control, and understanding of dopant activation mechanisms.
Lithography with Mask 2 (Gate Window Formation)
Lithography with Mask 2 (Gate Window Formation)
This lab involved defining gate regions for MOS structures. I spin-coated and baked photoresist, aligned Mask 2 using alignment marks, and exposed the wafer under UV light to pattern gate oxide openings. After development and post-bake, I etched the exposed oxide areas using buffered HF while monitoring etch completion visually under a microscope. This ensured clean and well-defined gate regions for subsequent oxidation.
Skills learned: Fine-alignment photolithography, gate window patterning, etch-rate estimation, and process inspection using optical microscopy.
Gate Oxidation and N₂ Anneal
Gate Oxidation and N₂ Anneal
The final lab focused on forming high-quality gate oxides for MOS capacitors. I cleaned the wafer using RCA steps and placed it in a dry oxidation furnace at 1000 °C with an oxygen flow of 400 sccm for 30 minutes, followed by nitrogen annealing for another 30 minutes. This process yielded thin, uniform SiO₂ films critical for MOSFET performance. The experiment concluded with ellipsometric thickness measurement and oxide quality verification.
Skills learned: Gate oxide growth, dry oxidation control, annealing for interface passivation, and film-quality analysis.
Born to Change the world
Born to Change the world
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