VLSI GATES AND MUXES
VLSI GATES AND MUXES
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I had embarked on an exciting and challenging journey to design and optimize logic gates and multiplexers in Cadence. This project, part of our VLSI design coursework, required me to deepen my understanding of transistor-level design, circuit simulation, and layout optimization. Through meticulous placement and routing, I ensured efficient power consumption, minimal propagation delay, and DRC/LVS compliance, reinforcing my skills in custom digital circuit design.
Inverter gate
Inverter gate
I designed and optimized a two-input circuit with an inverter gate in Cadence, ensuring efficient layout, minimal delay, and DRC/LVS compliance for VLSI design. The cell width is 4.8 micrometer.
Nand gate
Nand gate
I designed and optimized an NAND gate in Cadence, ensuring efficient layout, minimal delay, and DRC/LVS compliance for VLSI design. The cell width is 9.6 micrometer.
NOR gate
NOR gate
I designed and optimized an NOR gate in Cadence, ensuring efficient layout, minimal delay, and DRC/LVS compliance for VLSI design. The cell width is 7.2 micrometer.
XOR gate
XOR gate
I designed and optimized an XOR gate in Cadence, ensuring efficient layout, minimal delay, and DRC/LVS compliance for VLSI design. The cell width is 16.8 micrometer.
Schematic of XOR2 with only 6 transistors with non-restoring logic using pass gates
Schematic of XOR2 with a restoring logic
Layout of a XOR2 Gate with restoring logic
MUX21
MUX21
I designed and optimized an MUX21 gate in Cadence, ensuring efficient layout, minimal delay, and DRC/LVS compliance for VLSI design. The cell width is 12.3 micrometer.
Born to Change the world
Born to Change the world
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